1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device that features improved level of integration of a buried-gate semiconductor device, and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
FIG. 8 and FIG. 9 are cross-sectional views that show the process steps for manufacturing a MOSFET device as disclosed in the Japanese Unexamined Patent Publication No. 63-114174, Japanese Unexamined Patent Publication No. 2-194560, respectively.
First, as shown in FIG. 8 (a), an oxide film 202 pattern is formed on a silicon substrate 201, this being used as a mask to etch the silicon substrate, thereby forming a trench 203 as shown in FIG. 8 (b). Next, as shown in FIG. 8 (c), after forming a gate oxide film 204 on the surface of the substrate, the polysilicon film 205 and resist 206 are deposited over the entire surface. Then, the entire surface of the resist 206 and the polysilicon film 205 is etched, so as to have the polysilicon film remain inside the trench 203 only, this forming a gate electrode 207, as shown in FIG. 8 (d). Then, as shown in FIG. 8 (e), after forming a gate protective film 208 on the gate electrode 207, ion implantation of a dopant is done, so as to form a low-resistance layer 209, which will serve as a source and drain, on the surface of the silicon substrate. Then, as shown in FIG. 8 (f), an interlayer insulation film 210 is deposited on the substrate 201, after which via holes are formed and the metal wire 211 is formed to fill them and be contact with the source and drain.
Turning to FIG. 9, first as shown in FIG. 9 (a) a trench 303 is formed in a silicon substrate 301. Next, as shown in FIG. 9 (b), after forming a gate insulation film 304 on the substrate surface, polysilicon is deposited over the entire surface, and this is patterned so as to form a gate electrode 307. Then, as shown in FIG. 9 (c), the gate electrode 307 is used as a mask to perform ion implantation of a dopant, thereby forming an n-type diffusion layer 312, which will serve as a source and drain, on the surface of the substrate. Next, as shown in FIG. 9 (d), an interlayer insulation film 310 is deposited onto the substrate, after which via holes are formed and, as shown in FIG. 9 (e), a metal wire 311 is formed to fill them and be contact with the source and drain.
With a buried-gate type MOSFET fabricated as described above, as shown in the plan view of FIG. 10, in order to make a connection between the MOSFET gate electrodes 207 and 307 and the metal wire 320, it is necessary to have a region for a via hole 321 by widening the gate pattern on the outside of the diffusion layer 330 (on an isolation film), this representing a hindrance to achieving a high level of integration. Although in two examples of prior art as described above, a description of the plan views will be omitted, these have the same type of drawbacks as in a general type of MOSFET. With the device of FIG. 9, because of insufficient flatness on the surface of the interlayer insulation film, photolithography is problematic, because there is an insufficient focussing margin when performing metalization across step parts and reflections therefrom, this leads to such problems as incomplete etching, which can cause such problems as open or shorted wires.
The reason for the above is that, when a via hole, for the purpose of connecting a MOSFET gate electrode to a metal wire, is located in a channel region, in the case in which the gate length is approximately the same as the contact diameter, positioning offset causes a short circuit with the drain and source. Therefore, this via hole must inevitably be placed outside the diffusion layer, as shown in FIG. 7. Additionally, because a gate electrode or part thereof over the substrate forms a step thereon, the interlayer insulation film upper surface, reflecting this surface, loses its flatness.
Accordingly, it is an object of the present invention to improve over the drawbacks of the prior art as described above, by particularly providing a novel buried-gate type semiconductor device which enables the achievement of an interlayer insulation film with a flat upper surface, and which, by doing so, eliminates trouble such as opens and shorts in the interconnect layer, thereby improving yield. It is an additional object of the present invention to provide a method for manufacturing the above-noted semiconductor device.
Yet another object of the present invention is to provide a buried-gate type semiconductor device within improved level of integration, and a method for manufacturing such a semiconductor device.